The present invention relates to a lead frame having a wiring film obtained by laminating an insulating film on a lead pattern, a semiconductor package having a super multiple pin structure in which a semiconductor element (chip) is joined to the lead frame, and a method for manufacturing the lead frame and the semiconductor package.
The following semiconductor device is proposed by the applicant of this application. That is, a lead frame in which leads to be connected to electrodes of a semiconductor element at one end portions thereof are formed on one surface side of an insulating film, and further the external terminals connected to the other end portions of the leads are formed on the other surface side of the insulating film, is mounted on the semiconductor element, and a reinforcing outer ring surrounding the semiconductor element is formed at the outside of the semiconductor element.
However, in such a semiconductor device, it is indispensable to fill sealing agent in a gap between the outer ring and the semiconductor element after the outer ring surrounding the semiconductor element is disposed and the outer ring and the semiconductor element are positioned. The necessity of the positioning process obstructs the reduction in the number of fabrication processes of the semiconductor device. It is needless to say that this is a cause to obstruct the cost-down of the semiconductor device.
A semiconductor device which can solve the above problem has been proposed. FIG. 1 shows such a semiconductor device, wherein FIG. 1A is a plan view and FIG. 1B is an enlarged cross-sectional view which is taken along B--B line.
In FIGS. 1A and 1B, 1 represents a lead frame (film circuit), and reference numeral 2 represents an insulating film which serves as a base of the lead frame 1. 3 represents leads (wiring films) which are formed at one side (lower side) of the insulating film 2, and the tip portions 3a thereof are connected to electrode pads 5 of a semiconductor element 4. The leads 3 are formed by forming metal such as copper, nickel or the like by using as a mask a resist having a negative pattern to a pattern to be formed.
Reference numeral 6 represents ball-shaped outer terminals formed on the end portions 3b of the leads 3 which are located at the opposite side to the side which is connected to the electrode pads 5 of the semiconductor element 4, and the outer terminals are formed of nickel and soldering or gold. They are formed on a plane which is opposite to the semiconductor element side of the base (insulating film) 2, and connected to the end portions 3b of the leads 3 through holes of the base 2.
Reference numeral 8 represents a reinforcing outer ring which surrounds the semiconductor element 4, and it is formed integrally with the outside of the main portion of the lead frame through suspending portions 10. It has a laminate structure comprising copper, aluminum, copper, nickel or the like. The suspending portions 10 are formed of the same layers as the leads 3, and thus they are formed of copper or nickel, for example.
According to the above lead frame, as shown in FIG. 1A, the outer ring 8 is formed integrally with the outer portion of the main portion 15 of the lead frame through the suspending portions 10. Therefore, as shown in FIG. 1B, the ring 8 can be positioned to the semiconductor element 4 by merely mounting the lead frame 1 on the semiconductor element 4. Accordingly, no special process is needed to dispose the ring 8 in a predetermined positional relationship with the semiconductor element 4.
Accordingly, the number of fabrication steps of the semiconductor device can be reduced, and thus the manufacturing cost of the semiconductor device can be reduced.
In the case of the lead frame described above, the width of the suspending portions is narrow, and for example, it is equal to about 18 to 25 micrometers. Therefore, there is a problem that it is likely to be deformed under application of only a small impact during transportation or fabrication process because the mechanical strength thereof is low.
When the suspending portions of the lead frame are likely to be deformed as described above, the suspending portions are broken in the worst case and the circuit portion falls off, so that the yield is lowered. Further, when the suspending portions of the lead frame are likely to be deformed, the position precision between the circuit portion and the outer ring is lowered, so that a problem occurs in the fabrication process.
FIG. 2 shows a semiconductor package which can be mounted on a print wiring plate or the like through an organic substrate having external connection terminals such as solder balls or the like.
In FIG. 2, a semiconductor chip 51 is mounted on the surface of a multilayered organic wiring board 50 which is formed of organic material and comprises two to six layers. The electrode pads 50 of the semiconductor chip 51 and wiring films 52 are connected to each other by a wire bonding method using gold wires 53 or the like.
Solder balls (external connection terminals) 55 which are electrically connected via through-holes 54 to the wiring films 52 on the obverse surface are provided on the back surface of the multilayered organic wiring substrate 50, and the solder balls 55 are exposed from the open portion of a solder resist film 56 to the outside. The semiconductor chip 51 as well as the gold wires 53 is sealed by sealing resin 57.
In the semiconductor package 58 thus constructed, the solder balls 55 formed on the back surface are connected to the print wiring plate 59. The multilayered organic wiring board 50 is usually called as Ball Grid Array (BGA) because a number of solder balls 55 are arranged in a grid form, and the semiconductor package 58 using the multilayered organic wiring board 50 is called as BGA package.
However, in the above-described semiconductor package 58, the electrode pads of the semiconductor chip 51 and the wiring film 52 of the multilayered organic wiring substrate 50 are connected to each other by the wire bonding, and thus there is a limitation in the shortening of the wiring pitch. In other cases, for example, in a semiconductor package which is called as TCP (Table Carrier Package), a copper foil which is attached onto an insulating film base is etched to form leads, and thus there is such restriction that the leads are narrowed due to side etching. Therefore, there is also a limitation in the multiple-pin design.